This invention relates to a detector circuit for detecting a state change of an unknown binary signal during a prescribable time window, with at least one first flip-flop circuit receiving said unknown binary signal at its clock input and receiving a first window signal indicative of said time window at its signal input.
In intergrated circuit tester technology, it is a major problem to detect whether a certain binary signal is stable during a predefined time interval or whether it changes its state during that interval. The result of such a test is either "signal state" or "signal unstable". Such a test must be performed even with very short time windows and with a high repetition rate.
From German Patent No. 33 46 942, it is already known to apply a window signal to the D input of a D flip-flop, whereas the unknown binary signal is fed to the clock input of said flip-flop. Therefore, the unknown binary signal may trigger the flip-flop if a transition occurs during the predefined time window. A further flip-flop is used to detect transitions occurring during the rising or falling edge of the window signal, respectively.
Said known detector circuit can be used for applications where a limited repetition rate is sufficient. The repetition rate of the test (i.e., the repetition rate of the window signal) cannot be increased beyond a certain limit as the recovery time specified for each flip-flop does not allow to apply a further window signal before this recovery time is over.
It is a major objective of the present invention to provide a detector circuit which allows higher repetition rates of the window signal, i.e. higher testing rates.